When importing a project into Quartus 18.1 it helpfully suggests that it can rebuild the PLL IP blocks. Problem is, afterwards the MegaWizard doesn’t want to recognise the blocks anymore. It doesn’t even show an error, it just doesn’t do anything. As somebody who has never even used a MegaWizard before that was somewhat unfortunate.
Intel apparently wants to get rid of the Altera roots and the newly written block is called “PLL Intel FPGA IP” now instead of “Altera PLL”. Problem is, the MegaWizard doesn’t know about the new name. But it can be helped, just manually alter the file “pll_wizard.lst” in the “ip\altera\altera_pll” directory. Changes are in bold:
[Basic Functions|Clocks; PLLs and Resets|PLL] PLL Intel FPGA IP v18.1= "%t" "%w/../common/lib/megawizard.pl" --wizard:altera_pll --early_gen:on --wizard_file:"%w/source/top/pll_hw.tcl" --familyparameter:device_family %f %o %h <INFO> [...] <PINPLAN SUPPORTED="ON"/> <ALIAS>Altera PLL</ALIAS> <ALIAS>Altera PLL v10.0</ALIAS> <ALIAS>Altera PLL v10.1</ALIAS> [...] <ALIAS>Altera PLL v18.0</ALIAS> <ALIAS>Altera PLL v18.1</ALIAS> <ALIAS>PLL Intel FPGA IP v18.1</ALIAS> <ALIAS>PLL Intel FPGA IP v19.0</ALIAS> <ALIAS>PLL Intel FPGA IP v19.1</ALIAS> <ALIAS>PLL Intel FPGA IP v20.0</ALIAS> <ALIAS>PLL Intel FPGA IP v20.1</ALIAS> </INFO>
May this be of help to somebody.